1. Field of the Invention
The present invention relates to a memory device and to a method of controlling access to such a memory device. In particular, the present invention relates to techniques for controlling access to semiconductor memory devices, for example non-volatile devices such as Read Only Memory (ROM) devices, Flash devices, etc, or volatile devices such as Static Random Access Memory (SRAM), Dynamic RAM (DRAM), etc.
2. Description of the Prior Art
In such memory devices, a memory array is provided having a plurality of memory cells. Typically, the memory cells are arranged into a number of rows and columns, with the memory cells in a particular row being connected to a word line, and the memory cells in a particular column being connected to a bit line or a pair of bit lines.
In such memory devices, it is known to provide a number of redundant rows in order to increase yield. In particular, if it is determined that a particular row is faulty, then one of the redundant rows can be used in place of that faulty row. Typically, a storage is provided for keeping a record of any faulty rows, and the redundant row that should be used in its place. Such a storage will in particular keep a record of the address associated with each faulty row and an implicit or explicit identification of the redundant row to be used in place of that faulty row. The storage maintaining this information may in one embodiment take the form of one or more fuse or soft registers, a fuse register keeping its stored value after power is turned off, and a soft register losing its stored value after power is turned off.
For a memory device employing such redundant rows, then on receipt of each access request, irrespective of whether that access request specifies a read operation or a write operation, the address specified by that access request will be compared with the record of faulty rows and if it is determined that the specified address is seeking to access a faulty row, then the access will be arranged to proceed with respect to the identified redundant row. Otherwise, the access can proceed with respect to the addressed row. Due to the comparison of the address which needs to take place prior to the access proceeding, it will be appreciated that this gives rise to an increase in the memory access time for memory devices incorporating such redundant rows, when compared with the memory access time of an equivalent memory device not providing such redundant rows.
Hence, whilst it is beneficial to incorporate redundant rows within memory device designs in order to increase yield, it would be desirable to provide an improved access technique which enabled the memory access time to be reduced.